The present invention relates to static timing analysis of an integrated circuit design, and more specifically, to integration of functional analysis and common path pessimism removal in static timing analysis.
Timing analysis is performed during the various stages of digital integrated circuit design to ensure that timing requirements are met in every portion of the resulting integrated circuit or chip. Many known tests (e.g., setup test, hold test) may be performed as part of the timing analysis. The tests examine the worst-case scenario in most cases. Thus, for example, the setup test determines if the late mode arrival time at the input of a data node of a device is still earlier than the early mode arrival time at the clock node so that the data is captured correctly. Common path pessimism (CPP) is a source of pessimism or unnecessary timing penalty in timing analysis tests. CPP refers to the difference between the minimum and maximum delay (early mode and late mode) when two delays that are compared have a path in common. Early mode and late mode arrival times and delays result from variations in chip and environmental conditions. When the delay through a common path is computed assuming early mode in one case (e.g., for arrival time at the data node) and late mode in the other case (e.g., for arrival time at the clock node), the resulting test outcome is unnecessarily pessimistic, because two different chip or environmental conditions are assumed for the same path. In the case of a setup test, for example, if an edge (path) from the source node to the data node is the same as an edge from the source node to the clock node, then the early mode delay through that edge is considered for purposes of determining early mode arrival time at the clock node but the late mode delay through that same edge is considered for purposes of determining late mode arrival time at the data node. That is, different delays are assumed (with respect to each destination) for the same edge. Common path pessimism removal (CPPR) is a technique for adjusting timing slack (crediting some time back to the edge) to account for the CPP associated with the edge.